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  • IC芯片设计中ETM timing model lib文件有什么用?

    IC芯片设计中ETM timing model lib文件有什么用?

    ETM model 是hierarchical flow 中常用到的timing model, 通常一个block 都会有不同的工作模式,也会根据不同的工作模式分别抽取ETM model. 如今STA 工具都可以对ETM model 做merge,如Tempus 中的merge_model_timing, PT 中的merge_models. Merge 后一个ETM model (即一个.lib)中可以包含多个mode, 在做顶层实现或timing 分析时,可以根据当前的工作模式,来选择需要的mode, 通过mode 选择相应timing arc 的信息。

     

    描述:

    A library mode is a subset of active timing arcs that is defined in the timing library. Library modes are similar to conditional timing arcs, but do not require the application of constants to be set. Instead of changing a cell's mode by applying constants to its input pins, you can use this command to refer to sets of active arcs by name (such as READ or WRITE, for a memory cell).

    By default, all library modes in the timing library are active. If you specify one or more library modes using the set_mode command, only the timing arcs consistent with the specified mode(s) are active for the instance. All other library modes become inactive.

     

    示例:

    下面是一个lib 中某个pin 的简单描述,这段描述了pin-HAHA 在FUNC 跟 DFT 模式下的mim_pulse_width, 在lib 中用关键词 mode (etm_modes, mode_name) 来定义不同的模式,在上层实现或分析时,用命令 set_mode 来选择所需要的模式,如做FUNC 分析:

    set_mode FUNC [get_cells my_sub]

     

    pin (HAHA) {

    ...

    timing () { 

    related_pin: "feng_clock" ;

    timing_type: min_pulse_width ;

    mode(etm_modes,"FUNC");

    /* comment: from another design; */

    fall_constraint(scalar ){

    values ("0.024838");

    }

    timing () { 

    related_pin : "feng_clock" ;

    timing_type : min_pulse_width ;

    mode(etm_modes, "DFT");

    /* comment : from another design; */

    fall_constraint( scalar ){

    values ( "0.4838");

    }

    ...

    }

    常见问题:

    • 保证整个实现流程中SDC 的一致性,set_mode 应该不是一条标准的SDC 命令,所以不一定所有工具都可以将其写到SDC 中,但是当前几乎所有的实现及STA 工具都支持这条命令,所以最好在自己的工具端进行设置。

    • 如果设计中,有读多个mode 的ETM, 可以在工具中用命令report_mode 来report 这个ETM 对应instance 上所有的timing arc,以确保需要的arc 都被激活,不需要的arc 都被disable 掉。如果mode 设置不当,不止timing 不对,还可能引起其他奇怪的问题,如clock 不能propagate. 

     


    D:请教个问题,在hierarchy P&R流程中,当完成blockP&R后,会生成ILMInterface Logic Model),请问一下ILMabstraction timing module 有什么区别?

     

    GD:一个带了block里面的时序逻辑信息,一个没带,只有接口,我记得好像是这样。

    DB:ILMETM 只有sub module interface timing 信息,ABS 可以看到sub module 里面的timing.

    D:也就是说abs 带了block 里面的时序逻辑信息和interfacetiming信息,而ilm只有interfacetiming信息,就是说 abs.的信息包含ilm的信息?

     

    DB:我的理解是,从使用的目的性区分应该是两种不同类型的moduleabs是为了在pr tool 里看sub moudule timing更精准,代价是整体运行效率降低,因为信息量增大了。ilmetm没有那么精准,但是使用起来非常简单快速,效率高。

     

    ILM: The Interface Logic Model (ILM) is a technique to model blocks in hierarchal VLSI implementation flow. It is a gate level model of a physical block where only the connections from the inputsto the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model, including the flip-flops and the clock tree driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM. The advantage of ILM is that the entire path (clock to clock path) is visible at top level for interface nets, unlike traditional block-based hierarchal implementation flow. This gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

     

    ETM: The Extracted Timing Model (ETM) is an abstraction of the block using sequential andcombinational timing arcs. NLDM lookup tables are extracted for each of the timing arcs whosedelay is a function of input transitions and output loads, which makes the ETM usable withdifferent input transition times and different output loads. Using ETMs to abstract the timing model of a complex block or IP hides the detailed designimplementation information. This usage model is ideal for IP providers.

     

    ILM VS ETM: Both ETMs and ILMs can be used in a hierarchical static analysis flow when flat analysis isnot possible because of runtime and/or memory usage. An ILM offers more visibility intothe netlist, which can result in easier verification, but provides less IP protection. ETM is just like .lib means we have timing information till the pins not to the first level ( Imean to say the first gate of FF) but if we want to do timing analysis between the partitionlevel FF to FF then we can do that with ETM. ILM model we can see the timing logic to the first level and vise-versa from the last level tothe output pins but we can not optimize anything inside the partition.

     

     

     

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