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  • 数字IC设计笔试题详解——Cadence数字IC前端设计笔试题目

    数字IC设计笔试题详解——Cadence数字IC前端设计笔试题目

    数字IC笔试题(3)

        ——Cadence前端设计2018

    1、 What is the minimum number of flip flops to implement a state machine to detect the bit sequence 11011001 ?

    A.8      B.3        C.4          D.6

    状态机时序图如下,一共有9个状态,最少使用4个触发器

    2、 What types list below could be used in packed array ?

    A.Bit       B.int         C.logic    D.reg

    System Verilog 语法

    3、 Divide (1110111)2 by (1001)2

    A  Quotient (1101)2 remainder (10)2

    B. Quotient (1101)2 remainder (0)2

    C. Quotient (10)2 remainder (0)2

    D. Quotient (1101)2 remainder (101)2

    4、 What is the duration of task t ?  (仿真持续时间)

    A . 10 time units

    B. 16 time units

    C . 5 time units

    D . 7 time units

    Systemverilog  语法(fork-join、fork-join_none、fork_noin_any)

    5、 According to the following truth table with input A,B,C and D, what is an equation for output F ?

    D  (排除法,卡诺图化简)

    6、 What input can detect stuck at -1 fault at E ?

    A  (DFT 相关) 

     

    D= 1  C= 0  ,使得 Y = E = A&&B ,通过A选项输入,如果 Y = 1,则E stuck at 1

    7、 Given the following design ,What are the effective setup and hold times for the following circuit ?

    A.      Tsetup = 4ns, Thold = 1ns

    B.      Tsetup = 3ns, Thold = 0ns

    C.      Tsetup = 3ns, Thold = 1ns

    D.      Tsetup = 2ns, Thold = 0ns

    Setup分析 :

    D 触发器:

    增加数据路径异或门延时:

    增加数据路径异或门延时+ 时钟路径反相器延时

    Tsetup = 2ns + 2ns – 1ns = 3ns

     

     

     

    Hold分析 :

     

    D 触发器:

    增加数据路径异或门延时:

    增加数据路径异或门延时+ 时钟路径反相器延时

    Thold = 2ns – 2ns + 1ns = 1ns

    8、 What is the maximum operating frequency of the above circuit ? (第7题)

    A 250MHZ     B 80MHz        C 125 MHz     D 166.7MHz

    针对第7题的设计,Tskew = 0

     

    T – Tcq – Tlogic – T setup >= 0

    Tcq + Tlogic >= Thold

    T  >= 8ns ,Fmax = 125 M

    9、 Which equation best describes the maximum clock  frequency in a synchronous system ?

    D   同上题

    10、Given the following design ,What is the setup margin for flop2 ?

    A 8.95ns         B 9.55ns         C 0.85ns         D 7.75

    F2setup margin = 10ns – 0.65ns – 0.35ns - 0.45ns  + 0.6ns – 0.2ns = 8.95ns

    11、 What is the hold margin for flop2 ?

    A 0.5ns   B 0.1ns   C -0.1ns  D 9.9ns

     F2hold margin = 0.25ns + 0.15ns – 0.4ns - 0.1ns   = -0.1ns

    12、 Design a module in Verilog to satisfy the following requirements.

    (1)    A clock with the frequency of 100MHz

    (2)    A 4-bit width signal that sensitive at the clock posedge ,constrain this signal to be randomized 16 times in the range from 8 to 15.

    没有使用System verilog 语法

    13、What is logic systhesis ?

    逻辑综合是将RTL代码,进行翻译+ 优化 + 映射,生成特定工艺库相关的门级网表,用于后端的布局布线

    1、 What is function verification ?

    功能验证,用来验证设计的逻辑功能是否正确。

    2、 What is formal verification ?

    形式验证,使用静态穷举的方式验证电路。主要是用来验证电路经过逻辑综合,布局布线之后的逻辑等价性。

     

     

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